1. Field
Various features relate to a package on package (PoP) integrated device comprising several solder resist layers.
2. Background
FIG. 1 illustrates a conventional package on package (PoP) integrated device. As shown in FIG. 1, the integrated device 100 includes a first package 102 and a second package 104. The first package 102 includes a first substrate 106, a first die (e.g., chip) 108, a first set of solder balls 116, and a first set of interconnects 118. The first substrate 106 may include traces and/or vias (both of which are not shown). The second package 104 includes a second substrate 105, a second die 107, a third die 109, a second set of solder balls 115, a first set of wire bonding 117, and a second set of wire bonding 119. The second substrate 105 may include traces and/or vias (both of which are not shown). The second package 104 is positioned above the first package 102.
The first die 108 is coupled to a first surface (e.g., top surface) of the first substrate 106 through the first set of interconnects 118. The first set of solder balls 116 is coupled to a second surface (e.g., bottom surface) of the first substrate 106. The first substrate 106 includes a set of traces and/or vias that may electrically connect to the first die 108 and/or the first set of solder balls 116.
The second die 107 and the third die 109 are coupled to a first surface (e.g., top surface) of the second substrate 105. The second die 107 is electrically coupled to the traces and/or vias of the second substrate 105 through the first set of wire bonding 117. The third die 109 is electrically coupled to the traces and/or vias of the second substrate 105 through the second set of wire bonding 119. The second set of solder balls 115 is coupled to a second surface (e.g., bottom surface) of the second substrate 105.
One major drawback of the package on package (PoP) configuration shown in FIG. 1 is that it creates an integrated device with a form factor that may be too large for the needs of mobile computing devices. Specifically, the set of solder balls 115 are relatively large and thus cannot provide high density interconnects between packages. This may result in a package that is either too large and/or too thick. That is, the PoP configuration shown in FIG. 1 may be too thick and/or have a surface area that is too large to meet the needs and/or requirements of mobile computing devices.
Therefore, there is a need for an integrated device that includes an improved PoP configuration. Ideally, such an integrated device will have a better form factor (e.g., smaller, thinner) with high density interconnects between packages, while at the same time meeting the needs and/or requirements of mobile computing devices. Moreover, such an improved PoP configuration would provide better integrated device performance (e.g., better signal, better channel, better electrical speed performance).